This invention relates generally to integrated circuits, and more particularly to the design and layout of gate array integrated circuits.
Gate arrays comprise hundreds or thousands of gates which can be selectively coupled together to perform user-specified tasks. The gates are formed in matrixes in a semiconductor substrate as part of a "base set". An end-user can customize a gate array by adding metal connect layers over the base set to couple the gates into complex, logical circuits.
In FIGS. 1 and 2, a typical, prior art gate array 10 includes a gate region 12, driver regions 14, and bonding pad regions 16. As best seen in FIG. 2, the gate array 10 is formed over a semiconductor substrate 18 (usually silicon). A number or base set layers 20 in conjunction with active devices formed in the substrate 18, provide a large matrix of logical gates within the gate region 12. These gates typically include AND gates, OR gates, and inverters, as well as more complex logical functions. The construction and operation of the base set 21 (comprising the layers 20 and the substrate 18) is well known to those skilled in the art.
The base sets of gate arrays are manufactured in mass production quantities and are stored until desired by an end-user. The base sets are relatively low cost devices because they are produced in these large volumes. When end-users have a requirement for a customized logic circuit, customization layers 22 can be added over the base set 21 to cause the gate array 10 to perform the required logical functions. These customization layers typically include an oxide layer 24, a metal layer 26, an oxide layer 28, and a metal layer 30. As best seen in FIG. 1, the metal layer 26 comprises a number of parallel conductors 32, and the metal layer 30 includes a number of parallel conductors 34. By selectively coupling the conductors 32 and 34 to the base set 21 by conductive vias (not shown) through the oxide layers 24 and 28, the gates of the base set can be coupled together to perform the user-defined logical functions. Methods for designing and producing the customization layers 22 are well known to those skilled in the art.
The base set 21 includes a plurality of drivers 36 in the driver regions 14. It should be noted that the driver 36 in FIG. 2 is highly representational an actual driver would include active devices in the substrate 18 and interconnects in the layers 20. The drivers 36 am responsive to output signals developed within the gate array 10 and are operative to provide sufficient current to drive components external to the gate array 10. Each driver 36 of the base set 21 is coupled to a bonding pad 38 within bonding pad regions 16 by a via 40. These bonding pad are then coupled to leads of an integrated circuit package by any one of a number of well-known techniques such as wire bonding, tape automated bonding (TAB), flip-chip bonding, etc.
A particular base set can be used to produce logical circuits of varying complexity. Typically, the more complex the logical circuit, the more inputs and outputs are desired and, therefore, more bonding pads 38 are required. The number of bonding pads is increased by decreasing the "pitch" of the bonding pads, i.e. the center-to-center distance between adjacent bonding pads. However, the bonding pad pitch may be limited by the size of the gate array and by the bonding technique used. For example, a typical wire bond pitch may be 4.5 mils (thousandths of an inch), while a typical TAB bond pitch may be 4.0 mil.
Prior art drivers 36 are associated, one each, with the bonding pads 38. Therefore, the pitch of prior art drivers (i.e. the center-to-center distance between adjacent drivers 36) defines the pitch of the bonding pads 38. For example, if it is desirable to have bonding pad pitches at 4.8 mils and 4.5 mils for wire bonding and at 4.3 mils and 4.0 mils for TAB bonding, four different base sets 21 would be required, even if the gate array 10 were otherwise identical. Besides having to inventory four different base sets, the cost of each base set would be increased because fewer of each base set would be made.
The prior art has not, therefore, addressed the problem of providing a gate array base set which can accommodate a variable bonding pad pitch.